Design of a power management unit for a wireless-power-transfer-enabled wireless sensor node

• Main Author: Luo, Hao
• Other Authors: Siek Liter
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/137187
• Institution: Nanyang Technological University

Wireless Sensor Network (WSN) is one of the supporting technologies to materialize the Internet of Things (IoT). However, a large-scale deployment of the WSN faces multifarious challenges. WSN node size and maintenance cost incurred by periodic energy source replacement are among them. From the perspectives of energy sources, these two challenges can be better addressed by Wireless Power Transfer (WPT) technologies in comparison with energy-scavengers or traditional energy-storages. Omnidirectional-Electro-Magnetic (EM)-Radiation WPT-technology appears to be a viable choice. Hence, this work proposes various circuit design techniques in developing the dedicated Power Management Integrated Circuit (PMIC) structures to facilitate implementation of such WPT technology. In detail, this thesis lists (i) new trimming networks for a sub-1-volt CMOS Voltage Reference (VR), (ii) a load-adaptive negative-resistance at the input stage of an Operational Transconductance Amplifier (OTA) for an Capacitor-Less (OCL) Low Drop-Out Voltage Regulator (LDO), and (iii) a compensator-less Square Root Voltage Mode (SRVM) controller for a Pulse Width Modulation (PWM) Discontinuous Current Mode (DCM) Boost DC-DC Converter. To elaborate, the trimming networks aim at minimizing Temperature Coefficient (TC), which is enlarged due to process variations and finite resistance of the trimming switches in a CMOS Voltage Reference (VR). Moreover, the load-adaptive negative-resistance helps to boost the DC-gain of the proposed OCL-LDO while improving the current efficiency and ensuring fast-settling and frequency stability. Lastly, the compensator-less SRVM controller is meant to minimize power and area induced by discrete circuitries and components that build the compensator in a conventional DC-DC converter. Subsequently, structures of three key PMIC building blocks, such as a VR, an OCL-LDO and a boost DC-DC switching converter, are proposed making use of the aforementioned circuit design techniques. Trimming networks are proposed for a sub-1-volt CMOS VR that implements the threshold-voltage-difference (ΔVth) approach. Fabricated in 180-μm CMOS-technology, the trimmed CMOS VR consumes 0.94 μA under supply input of 0.8 V with a TC of 30 ppm/°C and a Power Supply Rejection (PSR) greater than -60 dB overall all frequencies. The trimmed VR operates under supply voltages from 0.7 V to 1.5 V. Furthermore, a fast-settling OCL-LDO that is enhanced by a load-adaptive negative-resistance is proposed. Such load-adaptive negative-resistance resides at the EA input-stage, which incorporates a Partial-Positive-Feedback (PPF). It eliminates the need for compensation capacitors for frequency stability while ensuring high accuracy and fast-settling. In detail, the overall OCL-LDO is manufactured in 180-μm CMOS-technology. It achieves a fast settling-time of 610 ns against a load step-up and -down between 0 and 50 mA in 100 ns. The OCL-LDO functions under supply voltages from 0.8 V to 1.5V. It consumes quiescent current of no more than 20 μA under no-load condition; it can source as much as 50 mA to the loading ICs. In addition, a compensator-less PWM Boost DC-DC converter in DCM based on a SRVM controller is also proposed. The SRVM controller achieves voltage regulation by implementing analog-signal-processing unit to sense the load current and convert it into a PWM voltage-control-signals to drive the power switches. The block-level design of the proposed Boost DC-DC converter is simulated in MATLAB. It achieves output ripples of 0.42% of its steady-state output of 3 V. Output overshoots of 3 mV with 4-μs recovery-time are observed during step-down load-transients from 40 mA to 0 mA in 100 ns. Correspondingly, output undershoots during step-up load-transients are less than 10.8 mV with recovery-time of 8.9 μs. The boost converter can start up from a 0.9-V input autonomously based on a proposed two-phase start-up control-scheme. On top of this, a novel signal-boosting-technique is presented to ensure gate-driving voltages for MOSFET switches as high as attainable to minimize conduction losses. At the steady-state, the boost converter operates with a fixed 1-MHz switching-frequency with a 1-μH inductor and a 10-μF capacitor to source load current up to 40 mA. Overall, all proposed designs achieve supply- and load-independence as well as power- and area-efficiency in addressing the unique PMIC design challenges dedicated to the Omnidirectional-EM-Radiation WPT.