Performance estimation of FPGA modules for modular design methodology using artificial neural network

• Main Authors: Herath, Kalindu, Prakash, Alok, Srikanthan, Thambipillai
• Other Authors: School of Computer Science and Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2020
• Subjects: Engineering::Computer science and engineering; FPGA; Floorplaning
• Online Access: https://hdl.handle.net/10356/139198
• Institution: Nanyang Technological University

Modern FPGAs consist of millions of logic resources allowing hardware designers to map increasingly large designs. However, the design productivity of mapping large designs is greatly affected by the long runtime of FPGA CAD flow. To mitigate it, modular design methodology has been introduced in the past that allows designers to partition large designs into smaller modules and compile & test the modules individually before assembling them together to complete the compilation process. Automated decision making on placing these modules on FPGA, however, is a slow and tedious process that requires large database of pre-compiled modules, which are compiled on a large number of placement positions. To accelerate this placement process during modular designing, in this paper we propose an ANN based performance estimation technique that can rapidly suggest the best shape and location for a given module. Experimental results on legacy as well as state-of-the-art FPGA devices show that the proposed technique can accurately estimate the Fmax of modules with an average error of less than 4%.