A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s hybrid analog equalizer under 21-dB channel loss in 65-nm CMOS

• Main Authors: Balachandran, Arya, Chen, Yong, Boon, Chirn Chye
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2020
• 主題: Engineering::Electrical and electronic engineering; Channel Loss; CMOS Equalizer
• 在線閱讀: https://hdl.handle.net/10356/139733
• 機構: Nanyang Technological University

Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a tripl...