Low power ADC design

• 主要作者: New, Jin Rui
• 其他作者: Chang Joseph
• 格式: Final Year Project
• 語言: English
• 出版: Nanyang Technological University 2020
• 主題: Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: https://hdl.handle.net/10356/140464

In this project, a single-bit first-order ΔΣ Analog to Digital Converter (ADC) using time-mode signal processing is proposed for use with a MEMS gyroscope application. The predominantly digital architecture of the design is able to take advantage of silicon semiconductor process scaling, thereby attaining improved performance, especially in terms of signal to noise ratio and power consumption. The key advantage of the current design over existing ΔΣ ADCs is the replacement of the loop filter with time-mode signal processing that uses digital circuitry. This simplifies design challenges associated with integrating analog and digital circuitry, improves the ease of scaling the design as the process node scales and reduces power consumption. System-level simulation is performed to determine specifications required for the ADC. Subsequently, individual time-mode signal processing blocks are designed at the circuit level in Cadence using a 40nm CMOS process from TSMC. Simulation results demonstrate that the proposed time-mode ΔΣ ADC has performance comparable to existing single-bit first order time-mode ΔΣ ADC designs and it is able to achieve a 10-bit resolution (SNDR=67dB) with a spurious free dynamic range of 68dB over the intended frequency range required for a typical gyroscope (3.5kHz to 7kHz) at a oversampling frequency of 10MHz while consuming approximately 64μW of power.