Efficient hardware accelerator for NORX authenticated encryption
Authenticated encryption with associated data (AEAD) plays a significant role in cryptography due to its ability to provide integrity, confidentiality and authenticity at the same time. There is an unceasing demand of high-performance and area-efficient AEAD ciphers due to the emergence of security...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2020
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/140597 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Authenticated encryption with associated data (AEAD) plays a significant role in cryptography due to its ability to provide integrity, confidentiality and authenticity at the same time. There is an unceasing demand of high-performance and area-efficient AEAD ciphers due to the emergence of security at the edge of computing fabric, such as, sensors and smartphone devices. Currently, a worldwide contest, titled CAESAR, is being held to decide on a set of AEAD ciphers, which are distinguished by their security, runtime performance, energy-efficiency and low area budget. In this paper, we focus on optimizing the hardware architecture of NORX by applying a pipeline technique. Our pre-layout results using commercial ASIC TSMC 65 technology library show that optimized NORX is 40.81% faster, 18.01% smaller, and improved the throughput per area by 76.9% when compared with state-of-the-art NORX implementation. |
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