Efficient hardware accelerator for NORX authenticated encryption

• Main Authors: Kumar, Sachin, Haj-Yahya, Jawad, Chattopadhyay, Anupam
• Other Authors: School of Computer Science and Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2020
• Subjects: Engineering::Computer science and engineering; Encryption; Hardware
• Online Access: https://hdl.handle.net/10356/140597
• Institution: Nanyang Technological University

Authenticated encryption with associated data (AEAD) plays a significant role in cryptography due to its ability to provide integrity, confidentiality and authenticity at the same time. There is an unceasing demand of high-performance and area-efficient AEAD ciphers due to the emergence of security at the edge of computing fabric, such as, sensors and smartphone devices. Currently, a worldwide contest, titled CAESAR, is being held to decide on a set of AEAD ciphers, which are distinguished by their security, runtime performance, energy-efficiency and low area budget. In this paper, we focus on optimizing the hardware architecture of NORX by applying a pipeline technique. Our pre-layout results using commercial ASIC TSMC 65 technology library show that optimized NORX is 40.81% faster, 18.01% smaller, and improved the throughput per area by 76.9% when compared with state-of-the-art NORX implementation.