Predictability and performance aware replacement policy PVISAM for unified shared caches in real-time multicores

• Main Authors: Mohammad Shihabul Haque, Arvind Easwaran
• Other Authors: School of Computer Science and Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Computer science and engineering; Cache Memory; Multicore Processing
• Online Access: https://hdl.handle.net/10356/140617
• Institution: Nanyang Technological University

Missing the deadline of an application task can be catastrophic in real-time systems. Therefore, to ensure timely completion of tasks, offline worst-case execution time and schedulability analysis is often performed for such real-time systems. One of the important inputs to this analysis is a safe u...