RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI
Results specific to power amplifiers (PAs) designed using a SOI EDNMOS transistor free of kinks in ID-VD plane and high breakdown voltage are presented. The suppression of the drain current kink and improvement in breakdown voltage are achieved by the omission of the N+ source implant step. Instead,...
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sg-ntu-dr.10356-1414672020-06-08T09:19:10Z RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI Toh, Rui Tze Ang, Diing Shenp Parthasarathy, Shyam Wong, Jen Shuang Yap, Hin Kiong Zhang, Shaoqiang School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering EDMOS Kink Effect Results specific to power amplifiers (PAs) designed using a SOI EDNMOS transistor free of kinks in ID-VD plane and high breakdown voltage are presented. The suppression of the drain current kink and improvement in breakdown voltage are achieved by the omission of the N+ source implant step. Instead, the source junction is realized by an optimized NLDD implant step only, allowing the formation of an under-source body contact. This approach is highly suitable for integration with RF switch and low-noise amplifiers on the same thin film SOI substrate. The improved channel conductance is found to give rise to highly linear amplitude and phase characteristics under high power conditions when the optimized EDNMOS device is used standalone as a PA. EDB (Economic Devt. Board, S’pore) 2020-06-08T09:19:09Z 2020-06-08T09:19:09Z 2018 Journal Article Toh, R. T., Ang, D. S., Parthasarathy, S., Wong, J. S., Yap, H. K., & Zhang, S. (2018). RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI. IEEE Electron Device Letters, 39(9), 1346-1349. doi:10.1109/LED.2018.2855442 0741-3106 https://hdl.handle.net/10356/141467 10.1109/LED.2018.2855442 2-s2.0-85050001948 9 39 1346 1349 en IEEE Electron Device Letters © 2018 IEEE. All rights reserved. |
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Engineering::Electrical and electronic engineering EDMOS Kink Effect Toh, Rui Tze Ang, Diing Shenp Parthasarathy, Shyam Wong, Jen Shuang Yap, Hin Kiong Zhang, Shaoqiang RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI |
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Results specific to power amplifiers (PAs) designed using a SOI EDNMOS transistor free of kinks in ID-VD plane and high breakdown voltage are presented. The suppression of the drain current kink and improvement in breakdown voltage are achieved by the omission of the N+ source implant step. Instead, the source junction is realized by an optimized NLDD implant step only, allowing the formation of an under-source body contact. This approach is highly suitable for integration with RF switch and low-noise amplifiers on the same thin film SOI substrate. The improved channel conductance is found to give rise to highly linear amplitude and phase characteristics under high power conditions when the optimized EDNMOS device is used standalone as a PA. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Toh, Rui Tze Ang, Diing Shenp Parthasarathy, Shyam Wong, Jen Shuang Yap, Hin Kiong Zhang, Shaoqiang |
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Article |
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Toh, Rui Tze Ang, Diing Shenp Parthasarathy, Shyam Wong, Jen Shuang Yap, Hin Kiong Zhang, Shaoqiang |
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Toh, Rui Tze |
title |
RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI |
title_short |
RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI |
title_full |
RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI |
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RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI |
title_full_unstemmed |
RF performance of a highly linear power amplifier EDNMOS transistor on trap-rich SOI |
title_sort |
rf performance of a highly linear power amplifier ednmos transistor on trap-rich soi |
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2020 |
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https://hdl.handle.net/10356/141467 |
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