A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers

A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers

This report presents a novel Simulink model of the All Digital Phase Locked Loop (ADPLL), which can be used in future developments if one wishes to design an ADPLL for a particular application. Also, a Gated Ring Oscillator-TDC was designed in 40nm CMOS, achieving a effective resolution of 0.73ps @...

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Main Author: Seah, Bryan Yun Da
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2020
Subjects:
Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/141878
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-141878
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spelling sg-ntu-dr.10356-1418782023-07-07T18:53:31Z A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers Seah, Bryan Yun Da Siek Liter School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems ELSIEK@ntu.edu.sg Engineering::Electrical and electronic engineering This report presents a novel Simulink model of the All Digital Phase Locked Loop (ADPLL), which can be used in future developments if one wishes to design an ADPLL for a particular application. Also, a Gated Ring Oscillator-TDC was designed in 40nm CMOS, achieving a effective resolution of 0.73ps @ 1MHz PLL Loop Bandwidth. Bachelor of Engineering (Electrical and Electronic Engineering) 2020-06-11T06:41:45Z 2020-06-11T06:41:45Z 2020 Final Year Project (FYP) https://hdl.handle.net/10356/141878 en A2167-191 application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
spellingShingle Engineering::Electrical and electronic engineering
Seah, Bryan Yun Da
A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers
description This report presents a novel Simulink model of the All Digital Phase Locked Loop (ADPLL), which can be used in future developments if one wishes to design an ADPLL for a particular application. Also, a Gated Ring Oscillator-TDC was designed in 40nm CMOS, achieving a effective resolution of 0.73ps @ 1MHz PLL Loop Bandwidth.
author2 Siek Liter
author_facet Siek Liter
Seah, Bryan Yun Da
format Final Year Project
author Seah, Bryan Yun Da
author_sort Seah, Bryan Yun Da
title A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers
title_short A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers
title_full A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers
title_fullStr A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers
title_full_unstemmed A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers
title_sort high resolution : low power gro-tdc for digital frac-n σ∆ frequency synthesizers
publisher Nanyang Technological University
publishDate 2020
url https://hdl.handle.net/10356/141878
_version_ 1772827343156412416

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