A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers

• 主要作者: Seah, Bryan Yun Da
• 其他作者: Siek Liter
• 格式: Final Year Project
• 語言: English
• 出版: Nanyang Technological University 2020
• 主題: Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/141878
• 機構: Nanyang Technological University

This report presents a novel Simulink model of the All Digital Phase Locked Loop (ADPLL), which can be used in future developments if one wishes to design an ADPLL for a particular application. Also, a Gated Ring Oscillator-TDC was designed in 40nm CMOS, achieving a effective resolution of 0.73ps @...