16-bit low power CMOS multiplier IC design

As technology evolves, FPGA has been used in every aspect of our lives, therefore, IC design is highly demanded in the market. Adders and multipliers are the fundamental arithmetic operators in IC design. To compare how efficient a multiplier is designed, low power consumption is one of the key poin...

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Main Author: Hu, Hang
Other Authors: Gwee Bah Hwee
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2020
Subjects:
Online Access:https://hdl.handle.net/10356/141919
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1419192023-07-07T18:06:54Z 16-bit low power CMOS multiplier IC design Hu, Hang Gwee Bah Hwee School of Electrical and Electronic Engineering ebhgwee@ntu.edu.sg Engineering::Electrical and electronic engineering As technology evolves, FPGA has been used in every aspect of our lives, therefore, IC design is highly demanded in the market. Adders and multipliers are the fundamental arithmetic operators in IC design. To compare how efficient a multiplier is designed, low power consumption is one of the key points we are looking at. This project aims to develop a multiplier using Verilog HDL, with different approaches (sequential multiplier and Braun multiplier). The developed multiplier is then evaluated and simulated to compare the power consumption. Bachelor of Engineering (Electrical and Electronic Engineering) 2020-06-11T11:25:51Z 2020-06-11T11:25:51Z 2020 Final Year Project (FYP) https://hdl.handle.net/10356/141919 en P2012-181 application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
spellingShingle Engineering::Electrical and electronic engineering
Hu, Hang
16-bit low power CMOS multiplier IC design
description As technology evolves, FPGA has been used in every aspect of our lives, therefore, IC design is highly demanded in the market. Adders and multipliers are the fundamental arithmetic operators in IC design. To compare how efficient a multiplier is designed, low power consumption is one of the key points we are looking at. This project aims to develop a multiplier using Verilog HDL, with different approaches (sequential multiplier and Braun multiplier). The developed multiplier is then evaluated and simulated to compare the power consumption.
author2 Gwee Bah Hwee
author_facet Gwee Bah Hwee
Hu, Hang
format Final Year Project
author Hu, Hang
author_sort Hu, Hang
title 16-bit low power CMOS multiplier IC design
title_short 16-bit low power CMOS multiplier IC design
title_full 16-bit low power CMOS multiplier IC design
title_fullStr 16-bit low power CMOS multiplier IC design
title_full_unstemmed 16-bit low power CMOS multiplier IC design
title_sort 16-bit low power cmos multiplier ic design
publisher Nanyang Technological University
publishDate 2020
url https://hdl.handle.net/10356/141919
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