A high speed 16-bit CMOS multiplier IC design
In this dissertation, we investigate some algorithms and use them to implement a 16-bit CMOS multiplier design. A variety of different adders are constructed from half adders and full adders. Meanwhile, a variety of multi-bit adders are used as the basis of the multiplier structure. All of them are...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
| Published: |
Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/154708 |
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| Institution: | Nanyang Technological University |
| Language: | English |