A high-throughput VLSI architecture for real-time full-HD gradient guided image filter

Guided image filtering has been applied widely in recent years as a solution to the ever-increasing demand of high-performance filtering, especially for real-time image/video processing. The lately proposed gradient domain guided image filter (GDGIF) is one of the typical works focusing on improving...

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Main Authors: Wu, Lei, Jong, Ching Chuen
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2020
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Online Access:https://hdl.handle.net/10356/142184
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1421842020-06-17T02:49:31Z A high-throughput VLSI architecture for real-time full-HD gradient guided image filter Wu, Lei Jong, Ching Chuen School of Electrical and Electronic Engineering VIRTUS IC Design Center of Excellence Engineering::Electrical and electronic engineering Guided Image Filter Image/video Processing Guided image filtering has been applied widely in recent years as a solution to the ever-increasing demand of high-performance filtering, especially for real-time image/video processing. The lately proposed gradient domain guided image filter (GDGIF) is one of the typical works focusing on improving the quality of the filtering result of the original guided image filter (GIF), dealing with the halo-artifacts problem for edge-preserving smoothing. However, due to the involvement of global pixel values in the computation, high computation complexity, and additional complex operation, there is no existing VLSI design for the gradient guided filter. This paper presents a high-throughput VLSI architecture for real-time full-HD (1920× 1080) GDGIF. Four techniques are used in the newly proposed design to reduce the computation complexity and increase the processing throughput. First, a pre-processing stage is introduced to address the problem of global parameters required in the GDGIF. Second, multi-scale down-samplings are adopted for reducing circuit size and processing time. Then, a parallel structure operated at a higher frequency is used at the output stage to restore the full image size and to achieve high throughput at the same time. At last, approximated computation is introduced to eliminate speed bottleneck by simplifying the complex exponentiation operation. Based on the STM 65-nm CMOS technology, the implementation results show that the proposed architecture is able to support full-HD image filtering at a throughput above 75 frame/s, with a design area of 586314 μm2 and a power consumption of 18.5 mW. 2020-06-17T02:49:31Z 2020-06-17T02:49:31Z 2018 Journal Article Wu, L., & Jong, C. C. (2019). A high-throughput VLSI architecture for real-time full-HD gradient guided image filter. IEEE Transactions on Circuits and Systems for Video Technology, 29(6), 1868-1877. doi:10.1109/TCSVT.2018.2852336 1051-8215 https://hdl.handle.net/10356/142184 10.1109/TCSVT.2018.2852336 2-s2.0-85049324915 6 29 1868 1877 en IEEE Transactions on Circuits and Systems for Video Technology © 2018 IEEE. All rights reserved.
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
Guided Image Filter
Image/video Processing
spellingShingle Engineering::Electrical and electronic engineering
Guided Image Filter
Image/video Processing
Wu, Lei
Jong, Ching Chuen
A high-throughput VLSI architecture for real-time full-HD gradient guided image filter
description Guided image filtering has been applied widely in recent years as a solution to the ever-increasing demand of high-performance filtering, especially for real-time image/video processing. The lately proposed gradient domain guided image filter (GDGIF) is one of the typical works focusing on improving the quality of the filtering result of the original guided image filter (GIF), dealing with the halo-artifacts problem for edge-preserving smoothing. However, due to the involvement of global pixel values in the computation, high computation complexity, and additional complex operation, there is no existing VLSI design for the gradient guided filter. This paper presents a high-throughput VLSI architecture for real-time full-HD (1920× 1080) GDGIF. Four techniques are used in the newly proposed design to reduce the computation complexity and increase the processing throughput. First, a pre-processing stage is introduced to address the problem of global parameters required in the GDGIF. Second, multi-scale down-samplings are adopted for reducing circuit size and processing time. Then, a parallel structure operated at a higher frequency is used at the output stage to restore the full image size and to achieve high throughput at the same time. At last, approximated computation is introduced to eliminate speed bottleneck by simplifying the complex exponentiation operation. Based on the STM 65-nm CMOS technology, the implementation results show that the proposed architecture is able to support full-HD image filtering at a throughput above 75 frame/s, with a design area of 586314 μm2 and a power consumption of 18.5 mW.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Wu, Lei
Jong, Ching Chuen
format Article
author Wu, Lei
Jong, Ching Chuen
author_sort Wu, Lei
title A high-throughput VLSI architecture for real-time full-HD gradient guided image filter
title_short A high-throughput VLSI architecture for real-time full-HD gradient guided image filter
title_full A high-throughput VLSI architecture for real-time full-HD gradient guided image filter
title_fullStr A high-throughput VLSI architecture for real-time full-HD gradient guided image filter
title_full_unstemmed A high-throughput VLSI architecture for real-time full-HD gradient guided image filter
title_sort high-throughput vlsi architecture for real-time full-hd gradient guided image filter
publishDate 2020
url https://hdl.handle.net/10356/142184
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