Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption
In this paper, we investigate the efficiency of FPGA implementations of AES and AES-like ciphers, specially in the context of authenticated encryption. We consider the encryption/decryption and the authentication/verification structures of OCB-like modes (like OTR or SCT modes). Their main advantage...
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sg-ntu-dr.10356-1429722020-07-17T00:44:20Z Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption Khairallah, Mustafa Chattopadhyay, Anupam Peyrin, Thomas School of Computer Science and Engineering School of Physical and Mathematical Sciences 18th International Conference on Cryptology in India 2017 Engineering::Computer science and engineering AES FPGA In this paper, we investigate the efficiency of FPGA implementations of AES and AES-like ciphers, specially in the context of authenticated encryption. We consider the encryption/decryption and the authentication/verification structures of OCB-like modes (like OTR or SCT modes). Their main advantage is that they are fully parallelisable. While this feature has already been used to increase the throughput/performance of hardware implementations, it is usually overlooked while comparing different ciphers. We show how to use it with zero area overhead, leading to a very significant efficiency gain. Additionally, we show that using FPGA technology mapping instead of logic optimization, the area of both the linear and non linear parts of the round function of several AES-like primitives can be reduced, without affecting the run-time performance. We provide the implementation results of two multi-stream implementations of both the LED and AES block ciphers. The AES implementation in this paper achieves an efficiency of 38 Mbps/slice, which is the most efficient implementation in literature, to the best of our knowledge. For LED, achieves 2.5 Mbps/slice on Spartan 3 FPGA, which is 2.57x better than the previous implementation. Besides, we use our new techniques to optimize the FPGA implementation of the CAESAR candidate Deoxys-I in both the encryption only and encryption/decryption settings. Finally, we show that the efficiency gains of the proposed techniques extend to other technologies, such as ASIC, as well. NRF (Natl Research Foundation, S’pore) 2020-07-17T00:44:20Z 2020-07-17T00:44:20Z 2017 Conference Paper Khairallah, M., Chattopadhyay, A., & Peyrin, T. (2017). Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption. Proceedings of the 18th International Conference on Cryptology in India 2017, 282-301. doi:10.1007/978-3-319-71667-1_15 978-3-319-71666-4 https://hdl.handle.net/10356/142972 10.1007/978-3-319-71667-1_15 2-s2.0-85037839583 282 301 en © 2017 Springer International Publishing AG. All rights reserved. |
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Engineering::Computer science and engineering AES FPGA Khairallah, Mustafa Chattopadhyay, Anupam Peyrin, Thomas Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption |
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In this paper, we investigate the efficiency of FPGA implementations of AES and AES-like ciphers, specially in the context of authenticated encryption. We consider the encryption/decryption and the authentication/verification structures of OCB-like modes (like OTR or SCT modes). Their main advantage is that they are fully parallelisable. While this feature has already been used to increase the throughput/performance of hardware implementations, it is usually overlooked while comparing different ciphers. We show how to use it with zero area overhead, leading to a very significant efficiency gain. Additionally, we show that using FPGA technology mapping instead of logic optimization, the area of both the linear and non linear parts of the round function of several AES-like primitives can be reduced, without affecting the run-time performance. We provide the implementation results of two multi-stream implementations of both the LED and AES block ciphers. The AES implementation in this paper achieves an efficiency of 38 Mbps/slice, which is the most efficient implementation in literature, to the best of our knowledge. For LED, achieves 2.5 Mbps/slice on Spartan 3 FPGA, which is 2.57x better than the previous implementation. Besides, we use our new techniques to optimize the FPGA implementation of the CAESAR candidate Deoxys-I in both the encryption only and encryption/decryption settings. Finally, we show that the efficiency gains of the proposed techniques extend to other technologies, such as ASIC, as well. |
author2 |
School of Computer Science and Engineering |
author_facet |
School of Computer Science and Engineering Khairallah, Mustafa Chattopadhyay, Anupam Peyrin, Thomas |
format |
Conference or Workshop Item |
author |
Khairallah, Mustafa Chattopadhyay, Anupam Peyrin, Thomas |
author_sort |
Khairallah, Mustafa |
title |
Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption |
title_short |
Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption |
title_full |
Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption |
title_fullStr |
Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption |
title_full_unstemmed |
Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption |
title_sort |
looting the luts : fpga optimization of aes and aes-like ciphers for authenticated encryption |
publishDate |
2020 |
url |
https://hdl.handle.net/10356/142972 |
_version_ |
1681059303303151616 |