Design of time-predictable architecture and DDR memory bank allocation for COTS multi-cores

• Main Author: Vasudevan, Sriram
• Other Authors: Arvind Easwaran
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Computer science and engineering::Computer systems organization::Processor architectures; Engineering::Computer science and engineering::Hardware::Memory structures
• Online Access: https://hdl.handle.net/10356/143308
• Institution: Nanyang Technological University

An increasing trend in the chip manufacturing industry is the adoption of multi-core processors. This overwhelming trend of using Commercial Off-The-Shelf (COTS) multi-core processors has benefited most of the industries that require high computing performance at low power and greater efficiency. H...