Design of time-predictable architecture and DDR memory bank allocation for COTS multi-cores
An increasing trend in the chip manufacturing industry is the adoption of multi-core processors. This overwhelming trend of using Commercial Off-The-Shelf (COTS) multi-core processors has benefited most of the industries that require high computing performance at low power and greater efficiency. H...
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Main Author: | Vasudevan, Sriram |
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Other Authors: | Arvind Easwaran |
Format: | Thesis-Doctor of Philosophy |
Language: | English |
Published: |
Nanyang Technological University
2020
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/143308 |
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Institution: | Nanyang Technological University |
Language: | English |
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