Power-balanced instruction scheduling for pipelined VLIW architectures

Power-balanced instruction scheduling for pipelined VLIW architectures

The focus of this thesis is on techniques for minimizing power variation for the duration of the whole program.

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Bibliographic Details
Main Author: Xiao, Shu
Other Authors: Lai Ming-Kit, Edmund
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
Online Access:https://hdl.handle.net/10356/2483
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Institution: Nanyang Technological University

Internet

https://hdl.handle.net/10356/2483

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