Power-balanced instruction scheduling for pipelined VLIW architectures
The focus of this thesis is on techniques for minimizing power variation for the duration of the whole program.
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sg-ntu-dr.10356-24832023-03-04T00:35:54Z Power-balanced instruction scheduling for pipelined VLIW architectures Xiao, Shu Lai Ming-Kit, Edmund School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures The focus of this thesis is on techniques for minimizing power variation for the duration of the whole program. DOCTOR OF PHILOSOPHY (SCE) 2008-09-17T09:03:58Z 2008-09-17T09:03:58Z 2006 2006 Thesis Xiao, S. (2006). Power-balanced instruction scheduling for pipelined VLIW architectures. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/2483 10.32657/10356/2483 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures Xiao, Shu Power-balanced instruction scheduling for pipelined VLIW architectures |
description |
The focus of this thesis is on techniques for minimizing power variation for the duration of the whole program. |
author2 |
Lai Ming-Kit, Edmund |
author_facet |
Lai Ming-Kit, Edmund Xiao, Shu |
format |
Theses and Dissertations |
author |
Xiao, Shu |
author_sort |
Xiao, Shu |
title |
Power-balanced instruction scheduling for pipelined VLIW architectures |
title_short |
Power-balanced instruction scheduling for pipelined VLIW architectures |
title_full |
Power-balanced instruction scheduling for pipelined VLIW architectures |
title_fullStr |
Power-balanced instruction scheduling for pipelined VLIW architectures |
title_full_unstemmed |
Power-balanced instruction scheduling for pipelined VLIW architectures |
title_sort |
power-balanced instruction scheduling for pipelined vliw architectures |
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2008 |
url |
https://hdl.handle.net/10356/2483 |
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1759856404719468544 |