Design of time-predictable architecture and DDR memory bank allocation for COTS multi-cores

• 主要作者: Vasudevan, Sriram
• 其他作者: Arvind Easwaran
• 格式: Thesis-Doctor of Philosophy
• 語言: English
• 出版: Nanyang Technological University 2020
• 主題: Engineering::Computer science and engineering::Computer systems organization::Processor architectures; Engineering::Computer science and engineering::Hardware::Memory structures
• 在線閱讀: https://hdl.handle.net/10356/143308

An increasing trend in the chip manufacturing industry is the adoption of multi-core processors. This overwhelming trend of using Commercial Off-The-Shelf (COTS) multi-core processors has benefited most of the industries that require high computing performance at low power and greater efficiency. H...