Hardware efficient approximate adder design

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas
• 其他作者: School of Computer Science and Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2020
• 主題: Engineering::Computer science and engineering::Hardware; Engineering::Electrical and electronic engineering::Integrated circuits; Approximate Computing; Computer Arithmetic
• 在線閱讀: https://hdl.handle.net/10356/143971
• 機構: Nanyang Technological University

This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the...