Reliable and modeling attack resistant authentication of Arbiter PUF in FPGA implementation with trinary quadruple response

• Main Authors: Zalivaka, Siarhei S., Ivaniuk, Alexander A., Chang, Chip Hong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering; Arbiter PUF; Reliability Enhancement
• Online Access: https://hdl.handle.net/10356/143997
• Institution: Nanyang Technological University

Field programmable gate array (FPGA) is a potential hotbed for malicious and counterfeit hardware infiltration. Arbiter-based physical unclonable function (A-PUF) has been widely regarded as a suitable lightweight security primitive for FPGA bitstream encryption and device authentication. Unfortunat...