Design and analysis of a low-noise regulated negative voltage generator system

• Main Author: Khanna, Devrishi
• Other Authors: Boon Chirn Chye
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/144061
• Institution: Nanyang Technological University

This thesis presents the design and analysis of a generic, low-noise regulated negative voltage generator, with wide tuning range and moderate driving capability. The highly integrated solution comprises of a multi-phase clock generator, fullyintegrated charge-pump and a regulator block while requiring only one off-chip capacitor that can be shared with supply decoupling capacitors. A novel analysis of the charge-pump module incorporating the effect of non-zero switch resistance and finite on-time of switches, is proposed, and a closed form expression of its output impedance is derived. The resulting frequency dependent charge-pump linear model is included in the regulator setup and utilized for the system level analysis and verification from both small and large signal prospective. This includes ascertaining the stability of the feedback loop, quantifying the charge-pump noise rejection by the regulator module and analysis of the complete settling profile from power-up till steady-state. In addition, the system level performance is further verified through rigorous transient co-simulation of the charge-pump and regulator modules. The overall solution is powered from a single 3.3V DC input and provides an output tuning range from -4.4V to +2.1V for biasing applications. The design also supports a maximum load current of 250µA, 550µA and 800µA for regulated output voltage at -3.0V, -1.5V and 1.5V respectively. The measured steady-state ripple is under 3mVP P while the noise voltage at the charge-pump operating frequency harmonics is below 130µVRMS and the noise-floor is under 5µVRMS. The design is also application verified with a Gallium-Nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180nm process, the prototype chip occupies an area of 0.55mm2. A systematic design methodology, supplemented with an in-depth analysis of CP and regulator modules, ensures robust implementation with reliable performance xioutput. An on-chip negative generator can facilitate the integration of alternate technologies with mainstream CMOS, besides allowing the designer to experiment with much wider range of circuits and applications. In this regard, the proposed negative voltage generator with low-noise output, wide-tuning and moderate driving capacity can cater to a wide range of integrated applications over multiple circuit design domains. Moreover, the design and analysis carried out in this work is useful towards the evolution of an on-chip negative voltage source that can be potentially included as a generic IP in future SOCs.