A dc-reactor-based solid-state fault current limiter for HVdc applications

A dc-reactor-based solid-state fault current limiter for HVdc applications

Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an...

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Bibliographic Details
Main Authors: Heidary, Amir, Radmanesh, Hamid, Rouzbehi, Kumars, Pou, Josep
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2020
Subjects:
Engineering::Electrical and electronic engineering
HVdc
Fault Current Limiters
Online Access:https://hdl.handle.net/10356/144517
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Institution: Nanyang Technological University
Language: English
Description
Summary:Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an innovative high inductance solid-state dc-reactor-based FCL (HISS-DCRFCL) to be used in HVdc applications. In fact, during the HISS-DCRFCL normal operation, its inductance value is extremely low, and its value becomes considerably high during the fault period, which decreases the fault current amplitude. The proposed HISS-DCRFCL performance is analyzed by MATLAB/Simulink and the simulation results are verified and confirmed by laboratory experimental results using a scaled-down laboratory prototype setup.

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