A dc-reactor-based solid-state fault current limiter for HVdc applications

Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an...

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Main Authors:	Heidary, Amir, Radmanesh, Hamid, Rouzbehi, Kumars, Pou, Josep
Other Authors:	School of Electrical and Electronic Engineering
Format:	Article
Language:	English
Published:	2020
Subjects:	Engineering::Electrical and electronic engineering HVdc Fault Current Limiters
Online Access:	https://hdl.handle.net/10356/144517
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Institution:	Nanyang Technological University
Language:	English

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spelling	sg-ntu-dr.10356-1445172020-11-10T08:44:30Z A dc-reactor-based solid-state fault current limiter for HVdc applications Heidary, Amir Radmanesh, Hamid Rouzbehi, Kumars Pou, Josep School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering HVdc Fault Current Limiters Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an innovative high inductance solid-state dc-reactor-based FCL (HISS-DCRFCL) to be used in HVdc applications. In fact, during the HISS-DCRFCL normal operation, its inductance value is extremely low, and its value becomes considerably high during the fault period, which decreases the fault current amplitude. The proposed HISS-DCRFCL performance is analyzed by MATLAB/Simulink and the simulation results are verified and confirmed by laboratory experimental results using a scaled-down laboratory prototype setup. Accepted version 2020-11-10T08:44:30Z 2020-11-10T08:44:30Z 2019 Journal Article Heidary, A., Radmanesh, H., Rouzbehi, K., & Pou, J. (2019). A dc-reactor-based solid-state fault current limiter for HVdc applications. IEEE Transactions on Power Delivery, 34(2), 720-728. doi:10.1109/tpwrd.2019.2894521 0885-8977 https://hdl.handle.net/10356/144517 10.1109/TPWRD.2019.2894521 2 34 720 728 en IEEE Transactions on Power Delivery © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TPWRD.2019.2894521. application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	Engineering::Electrical and electronic engineering HVdc Fault Current Limiters
spellingShingle	Engineering::Electrical and electronic engineering HVdc Fault Current Limiters Heidary, Amir Radmanesh, Hamid Rouzbehi, Kumars Pou, Josep A dc-reactor-based solid-state fault current limiter for HVdc applications
description	Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an innovative high inductance solid-state dc-reactor-based FCL (HISS-DCRFCL) to be used in HVdc applications. In fact, during the HISS-DCRFCL normal operation, its inductance value is extremely low, and its value becomes considerably high during the fault period, which decreases the fault current amplitude. The proposed HISS-DCRFCL performance is analyzed by MATLAB/Simulink and the simulation results are verified and confirmed by laboratory experimental results using a scaled-down laboratory prototype setup.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Heidary, Amir Radmanesh, Hamid Rouzbehi, Kumars Pou, Josep
format	Article
author	Heidary, Amir Radmanesh, Hamid Rouzbehi, Kumars Pou, Josep
author_sort	Heidary, Amir
title	A dc-reactor-based solid-state fault current limiter for HVdc applications
title_short	A dc-reactor-based solid-state fault current limiter for HVdc applications
title_full	A dc-reactor-based solid-state fault current limiter for HVdc applications
title_fullStr	A dc-reactor-based solid-state fault current limiter for HVdc applications
title_full_unstemmed	A dc-reactor-based solid-state fault current limiter for HVdc applications
title_sort	dc-reactor-based solid-state fault current limiter for hvdc applications
publishDate	2020
url	https://hdl.handle.net/10356/144517
_version_	1686109392262397952

A dc-reactor-based solid-state fault current limiter for HVdc applications

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