A carrier aggregation transmitter front end for 5-GHz WLAN 802.11ax application in 40-nm CMOS

• Main Authors: Liu, Bei, Yi, Xiang, Yang, Kaituo, Liang, Zhipeng, Feng, Guangyin, Choi, Pilsoon, Boon, Chirn Chye, Li, Chenyang
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2020
• Subjects: Engineering::Electrical and electronic engineering; Couplings; Transmitters
• Online Access: https://hdl.handle.net/10356/144772
• Institution: Nanyang Technological University

Carrier aggregation will be a key feature of the emerging 802.11ax system to boost data rate. Voltage-controlled oscillator (VCO) pulling and crosstalk between RF channels are two main problems related to carrier aggregation, which introduce severe impacts on adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM). To address these two problems, high isolation between transmitter channels is required, but may not be realizable in some practical cases due to the constraint of the layout. This article presents a transmitter front end that can support two-carrier aggregation for 802.11ax without high on-chip isolation. The proposed transmitter front end employs a parallel direct conversion and double conversion configuration, and two carriers are combined before the power amplifier (PA). In this way, the intrinsic problems of VCO pulling and crosstalk can be mitigated. The proposed transmitter front end was implemented in a 40-nm CMOS technology. For contiguous intraband carrier aggregation with VHT80, MCS9 signals [80-MHz bandwidth, 256-quadrature amplitude modulation (QAM), and 11.25-dB peak-to-average power ratio (PAPR)], the transmitter front end delivers an average output power of 5.3 + 4.8 dBm for two carriers with an EVM of ≤-32 dB, and the EVM can reach -36.1 dB.