Fast and cycle-accurate simulation of RTL NoC designs using test-driven cellular automata

Fast and cycle-accurate simulation of RTL NoC designs using test-driven cellular automata

Speeding up the register-transfer level (RTL) simulation of network-on-chip (NoC) is essential for design optimization under various use scenarios and parameters. One of the promising approaches for RTL NoC speedup is high-level modeling. Conventional high-level modeling approaches lead to an accura...

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Bibliographic Details
Main Authors: Seok, Moon Gi, Sarjoughian, Hessam S., Choi, Changbeom, Park, Daejin
Other Authors: School of Computer Science and Engineering
Format: Article
Language:English
Published: 2021
Subjects:
Engineering::Computer science and engineering
Network On Chip
Cellular Automata
Online Access:https://hdl.handle.net/10356/145879
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Institution: Nanyang Technological University
Language: English

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https://hdl.handle.net/10356/145879

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