Fast and cycle-accurate simulation of RTL NoC designs using test-driven cellular automata

• Main Authors: Seok, Moon Gi, Sarjoughian, Hessam S., Choi, Changbeom, Park, Daejin
• 其他作者: School of Computer Science and Engineering
• 格式: Article
• 語言: English
• 出版: 2021
• 主題: Engineering::Computer science and engineering; Network On Chip; Cellular Automata
• 在線閱讀: https://hdl.handle.net/10356/145879

Speeding up the register-transfer level (RTL) simulation of network-on-chip (NoC) is essential for design optimization under various use scenarios and parameters. One of the promising approaches for RTL NoC speedup is high-level modeling. Conventional high-level modeling approaches lead to an accura...