Neural network accelerator design using computing in memory

• Main Author: Seah, Leon Shin Yang
• Other Authors: Weichen Liu
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2021
• Subjects: Engineering::Computer science and engineering::Hardware::Memory structures
• Online Access: https://hdl.handle.net/10356/148415
• Institution: Nanyang Technological University

Image Processing has become an extremely popular field of application for Neural Networks. Convolution is a basic and critical operation for pattern recognition and breaking down images into feature maps. Similarly, “Deconvolution” is a critical step for constructing new data points out of given inputs for tasks such as image recovery in generative adversarial networks. With new emerging technology, Resistive Random-Access-Memory (ReRAM) based architectures have been widely tested and delivers good performance in accelerating the convolution operation through a process of “Computing-in-Memory”. The “Deconvolution” operation, however, still suffers from high overheads due to significant redundancies (>80%) involving zero-multiplications and/or incompatibility with the existing ReRAM based accelerator designs. In this project, we will explore various state-of-the-art Computing-in-Memory accelerator designs that have been proposed and focus our efforts on evaluating and implementing a design for a “Deconvolution” accelerator called RED.