Cross-VM micro-architectural covert channel attacks in L1 cache
In virtualized platforms, virtual machines are logically isolated by privileged hypervisors. These hypervisors provide abstraction and prevent virtual machines or processes from communicating with one another. Although the prevention of direct communication is enforced by these privileged hypervisor...
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| Format: | Final Year Project |
| Language: | English |
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Nanyang Technological University
2021
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| Online Access: | https://hdl.handle.net/10356/148686 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | In virtualized platforms, virtual machines are logically isolated by privileged hypervisors. These hypervisors provide abstraction and prevent virtual machines or processes from communicating with one another. Although the prevention of direct communication is enforced by these privileged hypervisors, these virtual machines or processes utilize the same hardware components like CPU core, CPU cache, bus, DRAM, etc. This sharing of hardware components opens up the possibility of two processes exchanging messages through what we call covert channels. In this paper, I would like to determine if the bandwidth L1 cache covert channels are useful in data exfiltration or are of any use to begin with, and compare it with L2 cache covert channels [1] |
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