16-bit low-power CMOS multiplier IC design

• Main Author: Zhang, Jingyao
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2021
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/149595
• Institution: Nanyang Technological University

To cope with the rapidly increasing demand of data processing and the world’s adoption of wireless devices, low power designs are becoming more and more important, especially in the wide-spread DSPs. As the most power-hungry component in DSPs, multipliers almost hog up all the power resources due to the heavy workload of multiplication. In this dissertation, several low-power techniques are used to design low-power multipliers, and eventually three 16-bit combinatorial multipliers and a 16-bit sequential multiplier are designed. In the combinatorial designs, an improved full adder cell design is compared to the full adder built with two half adders; two different approaches to signed multiplication are explored; and a carry save adder array multiplier is compared to the benchmark ripple carry adder array multiplier. In the sequential design, a Wallace tree structure is applied in the multiplier, and a stage controller is designed to enable the synchronous operation. In summary, the improved adder design and the carry save adder array contributed to the lower power consumption and the shorter delay of the multiplier, and the sequential Wallace tree multiplier further improves the power efficiency by eliminating unnecessary switching activities, and it introduced a flexible control over the balance of power and performance through the adjustment of clock speed.