Design a 16-bit low power delay multiplier

• Main Author: Lun, Yinghui
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2021
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/150272
• Institution: Nanyang Technological University

In this paper, a low power delay multiplier design is proposed. Aiming to achieve high performance, improvements has been done both in algorithm and architecture level. In algorithm level, a radix 4 modified Booth’s algorithm is applied to reduce the partial products for one half. And in the archite...