Design a 16-bit low power delay multiplier

• Main Author: Lun, Yinghui
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2021
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/150272
• Institution: Nanyang Technological University

In this paper, a low power delay multiplier design is proposed. Aiming to achieve high performance, improvements has been done both in algorithm and architecture level. In algorithm level, a radix 4 modified Booth’s algorithm is applied to reduce the partial products for one half. And in the architecture level, Dadda tree architecture tree is used.This kind of architecture can compress the accumulation process, reduce the delay time and save the number of adder cells. After using Verilog hardware descripti on language to set up the module, some softwar e such as Discovery Visualization Environment (DVE) GUI and design vision is used to do synthesis and simulation. The result shows that the proposed multiplier has achieved 33% in delay time and 38% in area, but the result also indicated that the power consumption has increased about 28% in total. This defect may be caused by the Dadda tree architecture which result a increase of the switching activities in the final stage.In conclusion, the proposed design has improved the performance of conventional multiplier. And there is also room for further improvement in every aspects of the low power delay multiplier design.