Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage

The market size of IoT devices is expanding rapidly as artificial intelligence and 5G technology are maturing. These smart portable devices require low power performance and a small chip area. The goal of this project is to design a 1.2V supply voltage rail-to-rail input and output operational ampli...

Full description

Saved in:
Bibliographic Details
Main Author: Ang, Kok Wai
Other Authors: Siek Liter
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2021
Subjects:
Online Access:https://hdl.handle.net/10356/149810
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-149810
record_format dspace
spelling sg-ntu-dr.10356-1498102023-07-07T17:53:51Z Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage Ang, Kok Wai Siek Liter School of Electrical and Electronic Engineering ELSIEK@ntu.edu.sg Engineering::Electrical and electronic engineering The market size of IoT devices is expanding rapidly as artificial intelligence and 5G technology are maturing. These smart portable devices require low power performance and a small chip area. The goal of this project is to design a 1.2V supply voltage rail-to-rail input and output operational amplifier with low noise performance. The technology node used in this project is GF 55nm CMOS process. The design in this project is a two-stage op-amp, which comprises a differential folded cascode amplifier with complementary input pair and a feedforward Class-AB output stage. A constant gm bias circuit with start-up circuitry is included in this project to provide the reference current to the op-amp. The challenges of this op-amp design are the undesired variation of input transconductance and the quiescent current of output transistors. The op-amp in this project has achieved a 9% input gm variation over the rail-to-rail common-mode input voltage using hex-pair input structure. The current consumption of op-amp in unity configuration with load (10kOhm and 10pF) is 148.3µA when input common-mode voltage is 0.6V. The input-referred noise voltage of the op-amp is 141.9nV/√Hz at 1 kHz frequency. The design also achieved a 77.9dB open-loop gain with a 77.2° phase margin at the unity-gain bandwidth of 3.10MHz. The open-loop gain is slightly low as the transistors have a large channel modulation index in this process. Bachelor of Engineering (Electrical and Electronic Engineering) 2021-06-09T05:36:37Z 2021-06-09T05:36:37Z 2021 Final Year Project (FYP) Ang, K. W. (2021). Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/149810 https://hdl.handle.net/10356/149810 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
spellingShingle Engineering::Electrical and electronic engineering
Ang, Kok Wai
Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage
description The market size of IoT devices is expanding rapidly as artificial intelligence and 5G technology are maturing. These smart portable devices require low power performance and a small chip area. The goal of this project is to design a 1.2V supply voltage rail-to-rail input and output operational amplifier with low noise performance. The technology node used in this project is GF 55nm CMOS process. The design in this project is a two-stage op-amp, which comprises a differential folded cascode amplifier with complementary input pair and a feedforward Class-AB output stage. A constant gm bias circuit with start-up circuitry is included in this project to provide the reference current to the op-amp. The challenges of this op-amp design are the undesired variation of input transconductance and the quiescent current of output transistors. The op-amp in this project has achieved a 9% input gm variation over the rail-to-rail common-mode input voltage using hex-pair input structure. The current consumption of op-amp in unity configuration with load (10kOhm and 10pF) is 148.3µA when input common-mode voltage is 0.6V. The input-referred noise voltage of the op-amp is 141.9nV/√Hz at 1 kHz frequency. The design also achieved a 77.9dB open-loop gain with a 77.2° phase margin at the unity-gain bandwidth of 3.10MHz. The open-loop gain is slightly low as the transistors have a large channel modulation index in this process.
author2 Siek Liter
author_facet Siek Liter
Ang, Kok Wai
format Final Year Project
author Ang, Kok Wai
author_sort Ang, Kok Wai
title Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage
title_short Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage
title_full Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage
title_fullStr Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage
title_full_unstemmed Design of low voltage low noise folded cascode CMOS op-amp with class AB output stage
title_sort design of low voltage low noise folded cascode cmos op-amp with class ab output stage
publisher Nanyang Technological University
publishDate 2021
url https://hdl.handle.net/10356/149810
_version_ 1772826473318580224