16 bits high speed CMOS multiplier IC design
High Speed VLSI circuits have become a key criterion for developing energy-efficient electronics for high-performance and portable applications. The multipliers are the most important component in designing an energy-efficient processor, as the multiplier design determines the efficiency. Half adder...
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Nanyang Technological University
2021
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sg-ntu-dr.10356-1502912023-07-07T18:20:49Z 16 bits high speed CMOS multiplier IC design Wut Yee Win Thoung Gwee Bah Hwee School of Electrical and Electronic Engineering ebhgwee@ntu.edu.sg Engineering::Electrical and electronic engineering::Electronic circuits High Speed VLSI circuits have become a key criterion for developing energy-efficient electronics for high-performance and portable applications. The multipliers are the most important component in designing an energy-efficient processor, as the multiplier design determines the efficiency. Half adders and complete adders are commonly used in digital multipliers and decreasing the number of adders reduces the multiplier's power dissipation. To execute partial product additions, the Wallace Tree Algorithm and Modified Booth Algorithm have been proposed in this project. For the final addition of partial products, the Ripple Carry Adder has been proposed. Bachelor of Engineering (Electrical and Electronic Engineering) 2021-06-13T11:26:51Z 2021-06-13T11:26:51Z 2021 Final Year Project (FYP) Wut Yee Win Thoung (2021). 16 bits high speed CMOS multiplier IC design. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/150291 https://hdl.handle.net/10356/150291 en application/pdf Nanyang Technological University |
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Engineering::Electrical and electronic engineering::Electronic circuits Wut Yee Win Thoung 16 bits high speed CMOS multiplier IC design |
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High Speed VLSI circuits have become a key criterion for developing energy-efficient electronics for high-performance and portable applications. The multipliers are the most important component in designing an energy-efficient processor, as the multiplier design determines the efficiency. Half adders and complete adders are commonly used in digital multipliers and decreasing the number of adders reduces the multiplier's power dissipation. To execute partial product additions, the Wallace Tree Algorithm and Modified Booth Algorithm have been proposed in this project. For the final addition of partial products, the Ripple Carry Adder has been proposed. |
| author2 |
Gwee Bah Hwee |
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Gwee Bah Hwee Wut Yee Win Thoung |
| format |
Final Year Project |
| author |
Wut Yee Win Thoung |
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Wut Yee Win Thoung |
| title |
16 bits high speed CMOS multiplier IC design |
| title_short |
16 bits high speed CMOS multiplier IC design |
| title_full |
16 bits high speed CMOS multiplier IC design |
| title_fullStr |
16 bits high speed CMOS multiplier IC design |
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16 bits high speed CMOS multiplier IC design |
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16 bits high speed cmos multiplier ic design |
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Nanyang Technological University |
| publishDate |
2021 |
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https://hdl.handle.net/10356/150291 |
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