Dual-hiding side-channel-attack resistant FPGA-based asynchronous-logic AES : design, countermeasures and evaluation

• Main Authors: Chong, Kwen-Siong, Ng, Jun-Sheng, Chen, Juncheng, Lwin, Ne Kyaw Zwa, Kyaw, Nay Aung, Ho, Weng-Geng, Chang, Joseph, Gwee, Bah-Hwee
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2021
• 主題: Engineering::Computer science and engineering::Hardware; Advanced Encryption Standard (AES); Asynchronous Circuits
• 在線閱讀: https://hdl.handle.net/10356/151198
• 機構: Nanyang Technological University

We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in t...