Area-time efficient two-dimensional reconfigurable integer DCT architecture for HEVC
In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be c...
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| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2021
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/151887 |
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| Institution: | Nanyang Technological University |
| Language: | English |