Novel edge comparator with input time hysteresis for improved edges arbitration

• Main Authors: Teh, Jian Sen, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Arbiters; Edge Comparator
• Online Access: https://hdl.handle.net/10356/152116
• Institution: Nanyang Technological University

Accurate edge arbitration between two input edges using arbiters or edge comparators is essential in the operation of various mixed-signal systems. However, unlike voltage comparators, input time hysteresis is difficult to be designed into edge comparators. This paper presents a novel edge comparator that has input time hysteresis effect, allowing it to be more robust against noise and jitter in repeated measurements. This was achieved using the SR latch memory effect, and two additional NMOS connected in a negative feedback manner. The proposed edge comparator was fabricated in a standard 0.18μm/1.8V CMOS technology. Simulation results shows a hysteresis window of 55fs. The SR latch memory effect and the presence of the input time hysteresis effect was verified by chip measurement.