Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting

This article presents a two-stage rectifier with novel DC-boosted gate bias for RF energy harvesting. The auxiliary gate bias enables rectifier to operate when input amplitude is smaller than its transistor threshold voltage while constraining the positive gate voltage during off state to reduce the...

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Main Authors: Lau, Wendy Wee Yee, Ho, Heng Wah, Siek Liter
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2021
Subjects:
Online Access:https://hdl.handle.net/10356/152174
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1521742021-08-05T00:49:08Z Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting Lau, Wendy Wee Yee Ho, Heng Wah Siek Liter School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering Energy Harvesting Rectifiers RF-DC Converters Deep Neural Network Deep Learning Design Automation Design Optimization This article presents a two-stage rectifier with novel DC-boosted gate bias for RF energy harvesting. The auxiliary gate bias enables rectifier to operate when input amplitude is smaller than its transistor threshold voltage while constraining the positive gate voltage during off state to reduce the reverse leakage current. An automated design optimization methodology using Deep Neural Network (DNN) to maximize efficiency is presented. The DNN is shown to accurately model SPICE simulated response of rectifier. Hence, the design phase turnaround time is minimized with fast prediction of optimized design parameters. The proposed rectifier has been fabricated in 65 nm standard CMOS technology. A maximum power conversion efficiency of 73.6% is measured at 2.45 GHz with input power of -6 dBm. The proposed rectifier has a measured sensitivity of -12 dBm for 1 V output voltage. Economic Development Board (EDB) This work was supported in part by the Singapore Economic Development Board (EDB) and in part by the GlobalFoundries Singapore Pte. Ltd 2021-08-05T00:47:56Z 2021-08-05T00:47:56Z 2020 Journal Article Lau, W. W. Y., Ho, H. W. & Siek Liter (2020). Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting. IEEE Transactions On Circuits and Systems I: Regular Papers, 67(12), 4322-4333. https://dx.doi.org/10.1109/TCSI.2020.3022280 1549-8328 https://hdl.handle.net/10356/152174 10.1109/TCSI.2020.3022280 12 67 4322 4333 en IEEE Transactions on Circuits and Systems I: Regular Papers © 2020 IEEE. All rights reserved.
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
Energy Harvesting
Rectifiers
RF-DC Converters
Deep Neural Network
Deep Learning
Design Automation
Design Optimization
spellingShingle Engineering::Electrical and electronic engineering
Energy Harvesting
Rectifiers
RF-DC Converters
Deep Neural Network
Deep Learning
Design Automation
Design Optimization
Lau, Wendy Wee Yee
Ho, Heng Wah
Siek Liter
Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting
description This article presents a two-stage rectifier with novel DC-boosted gate bias for RF energy harvesting. The auxiliary gate bias enables rectifier to operate when input amplitude is smaller than its transistor threshold voltage while constraining the positive gate voltage during off state to reduce the reverse leakage current. An automated design optimization methodology using Deep Neural Network (DNN) to maximize efficiency is presented. The DNN is shown to accurately model SPICE simulated response of rectifier. Hence, the design phase turnaround time is minimized with fast prediction of optimized design parameters. The proposed rectifier has been fabricated in 65 nm standard CMOS technology. A maximum power conversion efficiency of 73.6% is measured at 2.45 GHz with input power of -6 dBm. The proposed rectifier has a measured sensitivity of -12 dBm for 1 V output voltage.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Lau, Wendy Wee Yee
Ho, Heng Wah
Siek Liter
format Article
author Lau, Wendy Wee Yee
Ho, Heng Wah
Siek Liter
author_sort Lau, Wendy Wee Yee
title Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting
title_short Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting
title_full Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting
title_fullStr Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting
title_full_unstemmed Deep Neural Network (DNN) optimized design of 2.45 GHz CMOS rectifier with 73.6% peak efficiency for RF energy harvesting
title_sort deep neural network (dnn) optimized design of 2.45 ghz cmos rectifier with 73.6% peak efficiency for rf energy harvesting
publishDate 2021
url https://hdl.handle.net/10356/152174
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