A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS

As technology scales, integrating high resolution ADCs into high fidelity mixed signal systems becomes challenging in advanced CMOS processes. Cascading integrators to achieve high-order filter structures limits the modulation index and compromises on stability at the expense of added hardware and p...

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Main Authors: Leow, Yoon Hwee, Tang, Howard, Sun, Zhuochao, Siek, Liter
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2021
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Online Access:https://hdl.handle.net/10356/152236
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1522362021-08-05T02:48:23Z A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS Leow, Yoon Hwee Tang, Howard Sun, Zhuochao Siek, Liter School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Engineering::Computer science and engineering Continuous-time Delta-Sigma Low Voltage Noise-coupled NTF Enhancement Successive Approximation As technology scales, integrating high resolution ADCs into high fidelity mixed signal systems becomes challenging in advanced CMOS processes. Cascading integrators to achieve high-order filter structures limits the modulation index and compromises on stability at the expense of added hardware and power consumption. To optimize the maximum stable amplitude (MSA) to accommodate a larger input dynamic range, the supply rails have to be expanded, which limited technology choices to those of a larger feature size. This work proposes a 25 kHz 3rd-order continuous-time ΔΣ modulator (CTΔΣM) utilizing a 5-bit SAR quantizer, enabling noise coupling (NC) to be possible in a typical nanoscale CMOS 65 nm technology with VDD of 1 V. Mismatches in SAR comparator and DAC array are mitigated with a proposed calibration scheme while CM mismatches are solved by a floating differential charge storage capacitor (FDCSC) coupling method. To allow sufficient time for SAR bit cycling and noise charge feedback settling, 1 Ts excess loop delay (ELD) is compensated with digital differentiation that minimizes both the power and complexity of the auxiliary feedback DAC. The prototype obtained DR/SNR/SNDR of 103.1 dB/100.1 dB/95.2 dB while dissipating 0.8 mW, hence achieving a FoMSNDR and FoMschreier of 0.34 pJ/level and 177.9 dB, respectively. 2021-08-05T02:46:04Z 2021-08-05T02:46:04Z 2016 Journal Article Leow, Y. H., Tang, H., Sun, Z. & Siek, L. (2016). A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 51(11), 2625-2638. https://dx.doi.org/10.1109/JSSC.2016.2593777 0018-9200 https://hdl.handle.net/10356/152236 10.1109/JSSC.2016.2593777 11 51 2625 2638 en IEEE Journal of Solid-State Circuits © 2016 IEEE. All rights reserved.
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Computer science and engineering
Continuous-time
Delta-Sigma
Low Voltage
Noise-coupled
NTF Enhancement
Successive Approximation
spellingShingle Engineering::Computer science and engineering
Continuous-time
Delta-Sigma
Low Voltage
Noise-coupled
NTF Enhancement
Successive Approximation
Leow, Yoon Hwee
Tang, Howard
Sun, Zhuochao
Siek, Liter
A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS
description As technology scales, integrating high resolution ADCs into high fidelity mixed signal systems becomes challenging in advanced CMOS processes. Cascading integrators to achieve high-order filter structures limits the modulation index and compromises on stability at the expense of added hardware and power consumption. To optimize the maximum stable amplitude (MSA) to accommodate a larger input dynamic range, the supply rails have to be expanded, which limited technology choices to those of a larger feature size. This work proposes a 25 kHz 3rd-order continuous-time ΔΣ modulator (CTΔΣM) utilizing a 5-bit SAR quantizer, enabling noise coupling (NC) to be possible in a typical nanoscale CMOS 65 nm technology with VDD of 1 V. Mismatches in SAR comparator and DAC array are mitigated with a proposed calibration scheme while CM mismatches are solved by a floating differential charge storage capacitor (FDCSC) coupling method. To allow sufficient time for SAR bit cycling and noise charge feedback settling, 1 Ts excess loop delay (ELD) is compensated with digital differentiation that minimizes both the power and complexity of the auxiliary feedback DAC. The prototype obtained DR/SNR/SNDR of 103.1 dB/100.1 dB/95.2 dB while dissipating 0.8 mW, hence achieving a FoMSNDR and FoMschreier of 0.34 pJ/level and 177.9 dB, respectively.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Leow, Yoon Hwee
Tang, Howard
Sun, Zhuochao
Siek, Liter
format Article
author Leow, Yoon Hwee
Tang, Howard
Sun, Zhuochao
Siek, Liter
author_sort Leow, Yoon Hwee
title A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS
title_short A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS
title_full A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS
title_fullStr A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS
title_full_unstemmed A 1 V 103 dB 3rd-order audio continuous-time ΔΣ ADC with enhanced noise shaping in 65 nm CMOS
title_sort 1 v 103 db 3rd-order audio continuous-time δσ adc with enhanced noise shaping in 65 nm cmos
publishDate 2021
url https://hdl.handle.net/10356/152236
_version_ 1707774592829882368