An unclocked analog-to-digital converter

An unclocked A/D technique using a serial chain of comparators in its speed limiting path is described. The design fabricated in 2 μm double-metal single-polysilicon p-well CMOS technology occupies an area of 1.67 mm×1.67 mm, produces an 8-bit conversion in<1 μs and consumes a power of 40 mW.

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Bibliographic Details
Main Authors:	Siek, Liter, Graham, Rigby
Other Authors:	School of Electrical and Electronic Engineering
Format:	Conference or Workshop Item
Language:	English
Published:	2021
Subjects:	Engineering::Electrical and electronic engineering High Speed ADC Unclocked A/D Technique Analog-to-Digital Converter
Online Access:	https://trove.nla.gov.au/work/18049131 https://hdl.handle.net/10356/152451
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Institution:	Nanyang Technological University
Language:	English

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spelling	sg-ntu-dr.10356-1524512021-08-23T07:26:20Z An unclocked analog-to-digital converter Siek, Liter Graham, Rigby School of Electrical and Electronic Engineering 9th Australian Microelectronics Conference: 'Foundation for the future' VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering High Speed ADC Unclocked A/D Technique Analog-to-Digital Converter An unclocked A/D technique using a serial chain of comparators in its speed limiting path is described. The design fabricated in 2 μm double-metal single-polysilicon p-well CMOS technology occupies an area of 1.67 mm×1.67 mm, produces an 8-bit conversion in<1 μs and consumes a power of 40 mW. 2021-08-23T07:24:25Z 2021-08-23T07:24:25Z 1990 Conference Paper Siek, L. & Graham, R. (1990). An unclocked analog-to-digital converter. 9th Australian Microelectronics Conference: 'Foundation for the future', 339-344. 0909394202 https://trove.nla.gov.au/work/18049131 https://hdl.handle.net/10356/152451 339 344 en © 1990 Institution of Radio and Electronics Engineers Australia. All rights reserved.
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	Engineering::Electrical and electronic engineering High Speed ADC Unclocked A/D Technique Analog-to-Digital Converter
spellingShingle	Engineering::Electrical and electronic engineering High Speed ADC Unclocked A/D Technique Analog-to-Digital Converter Siek, Liter Graham, Rigby An unclocked analog-to-digital converter
description	An unclocked A/D technique using a serial chain of comparators in its speed limiting path is described. The design fabricated in 2 μm double-metal single-polysilicon p-well CMOS technology occupies an area of 1.67 mm×1.67 mm, produces an 8-bit conversion in<1 μs and consumes a power of 40 mW.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Siek, Liter Graham, Rigby
format	Conference or Workshop Item
author	Siek, Liter Graham, Rigby
author_sort	Siek, Liter
title	An unclocked analog-to-digital converter
title_short	An unclocked analog-to-digital converter
title_full	An unclocked analog-to-digital converter
title_fullStr	An unclocked analog-to-digital converter
title_full_unstemmed	An unclocked analog-to-digital converter
title_sort	unclocked analog-to-digital converter
publishDate	2021
url	https://trove.nla.gov.au/work/18049131 https://hdl.handle.net/10356/152451
_version_	1709685315086581760

An unclocked analog-to-digital converter

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