An unclocked analog-to-digital converter
An unclocked A/D technique using a serial chain of comparators in its speed limiting path is described. The design fabricated in 2 μm double-metal single-polysilicon p-well CMOS technology occupies an area of 1.67 mm×1.67 mm, produces an 8-bit conversion in<1 μs and consumes a power of 40 mW.
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Main Authors: | Siek, Liter, Graham, Rigby |
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Other Authors: | School of Electrical and Electronic Engineering |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2021
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Subjects: | |
Online Access: | https://trove.nla.gov.au/work/18049131 https://hdl.handle.net/10356/152451 |
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Institution: | Nanyang Technological University |
Language: | English |
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