A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220...
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Main Authors: | , , , |
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Other Authors: | |
Format: | Conference or Workshop Item |
Language: | English |
Published: |
2021
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/152100 |
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Institution: | Nanyang Technological University |
Language: | English |