A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS

• Main Authors: Chacón, Oscar Morales, Wikner, Jacob, Alvandpour, Atila, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; 5G; Current-steering; Digital-to-Analog Converter; High Speed; CMOS; Radio Frequency; Low Power
• Online Access: https://hdl.handle.net/10356/152100
• Institution: Nanyang Technological University

Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220...