A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS

A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS

Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220...

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Main Authors: Chacón, Oscar Morales, Wikner, Jacob, Alvandpour, Atila, Siek, Liter
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2021
Subjects:
Engineering::Electrical and electronic engineering
5G
Current-steering
Digital-to-Analog Converter
High Speed
CMOS
Radio Frequency
Low Power
Online Access:https://hdl.handle.net/10356/152100
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1521002022-07-22T07:20:14Z A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS Chacón, Oscar Morales Wikner, Jacob Alvandpour, Atila Siek, Liter School of Electrical and Electronic Engineering 2020 IEEE Nordic Circuits and Systems Conference (NorCAS) VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering 5G Current-steering Digital-to-Analog Converter High Speed CMOS Radio Frequency Low Power Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220 mW for 58.6-pJ energy consumption per sample. This work is financially supported by the Sweden’s innovation agency (VINNOVA) under project 2017-04891 as well as the strategic research environment funded by the Swedish government (ELLIIT). 2021-07-16T01:13:46Z 2021-07-16T01:13:46Z 2020 Conference Paper Chacón, O. M., Wikner, J., Alvandpour, A. & Siek, L. (2020). A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS. 2020 IEEE Nordic Circuits and Systems Conference (NorCAS). https://dx.doi.org/10.1109/NorCAS51424.2020.9265003 978-1-7281-9227-7 https://hdl.handle.net/10356/152100 10.1109/NorCAS51424.2020.9265003 en © 2020 IEEE. All rights reserved.
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
5G
Current-steering
Digital-to-Analog Converter
High Speed
CMOS
Radio Frequency
Low Power
spellingShingle Engineering::Electrical and electronic engineering
5G
Current-steering
Digital-to-Analog Converter
High Speed
CMOS
Radio Frequency
Low Power
Chacón, Oscar Morales
Wikner, Jacob
Alvandpour, Atila
Siek, Liter
A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
description Exploring the simplicity and scalability of binary-weighted architectures, this paper presents a 10-bit high-speed current-steering digital-to-analog converter (DAC) designed in 65-nm CMOS technology. Post-layout simulations show that the DAC achieves 3.75-GHz sampling frequency while consuming 220 mW for 58.6-pJ energy consumption per sample.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Chacón, Oscar Morales
Wikner, Jacob
Alvandpour, Atila
Siek, Liter
format Conference or Workshop Item
author Chacón, Oscar Morales
Wikner, Jacob
Alvandpour, Atila
Siek, Liter
author_sort Chacón, Oscar Morales
title A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
title_short A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
title_full A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
title_fullStr A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
title_full_unstemmed A 10-bit 3.75-GS/s binary-weighted DAC with 58.6-pJ energy consumption in 65-nm CMOS
title_sort 10-bit 3.75-gs/s binary-weighted dac with 58.6-pj energy consumption in 65-nm cmos
publishDate 2021
url https://hdl.handle.net/10356/152100
_version_ 1739837407873728512

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