Gate-level static approximate adders : a comparative analysis
Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off betwee...
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sg-ntu-dr.10356-1534022021-12-02T02:13:09Z Gate-level static approximate adders : a comparative analysis Balasubramanian, Padmanabhan Nayar, Raunaq Maskell, Douglas Leslie School of Computer Science and Engineering Hardware & Embedded Systems Lab (HESL) Engineering::Computer science and engineering Engineering::Electrical and electronic engineering Approximate Computing Approximate Adder Digital Circuits Arithmetic Circuits Low Power Design VLSI Design Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable. Ministry of Education (MOE) Published version This research was funded by the Ministry of Education (MOE), Singapore under an academic research fund Tier-2 grant number MOE2018-T2-2-024. 2021-12-02T02:13:09Z 2021-12-02T02:13:09Z 2021 Journal Article Balasubramanian, P., Nayar, R. & Maskell, D. L. (2021). Gate-level static approximate adders : a comparative analysis. Electronics, 10(23), 2917-. https://dx.doi.org/10.3390/electronics10232917 2079-9292 https://hdl.handle.net/10356/153402 10.3390/electronics10232917 23 10 2917 en MOE2018-T2-2-024 Electronics © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). application/pdf |
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Engineering::Computer science and engineering Engineering::Electrical and electronic engineering Approximate Computing Approximate Adder Digital Circuits Arithmetic Circuits Low Power Design VLSI Design Balasubramanian, Padmanabhan Nayar, Raunaq Maskell, Douglas Leslie Gate-level static approximate adders : a comparative analysis |
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Approximate or inaccurate addition is found to be viable for practical applications which have an inherent error tolerance. Approximate addition is realized using an approximate adder, and many approximate adder designs have been put forward in the literature targeting an acceptable trade-off between quality of results and savings in design metrics compared to the accurate adder. Approximate adders can be classified into three categories as: (a) suitable for FPGA implementation, (b) suitable for ASIC type implementation, and (c) suitable for FPGA and ASIC type implementations. Among these, approximate adders, which are suitable for FPGA and ASIC type implementations are particularly interesting given their versatility and they are typically designed at the gate level. Depending on the way approximation is built into an approximate adder, approximate adders can be classified into two kinds as static approximate adders and dynamic approximate adders. This paper compares and analyzes static approximate adders which are suitable for both FPGA and ASIC type implementations. We consider many static approximate adders and evaluate their performance for a digital image processing application using standard figures of merit such as peak signal to noise ratio and structural similarity index metric. We provide the error metrics of approximate adders, and the design metrics of accurate and approximate adders corresponding to FPGA and ASIC type implementations. For the FPGA implementation, we considered a Xilinx Artix-7 FPGA, and for an ASIC type implementation, we considered a 32/28 nm CMOS standard digital cell library. While the inferences from this work could serve as a useful reference to determine an optimum static approximate adder for a practical application, in particular, we found approximate adders HOAANED, HERLOA and M-HERLOA to be preferable. |
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School of Computer Science and Engineering |
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School of Computer Science and Engineering Balasubramanian, Padmanabhan Nayar, Raunaq Maskell, Douglas Leslie |
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Article |
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Balasubramanian, Padmanabhan Nayar, Raunaq Maskell, Douglas Leslie |
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Balasubramanian, Padmanabhan |
title |
Gate-level static approximate adders : a comparative analysis |
title_short |
Gate-level static approximate adders : a comparative analysis |
title_full |
Gate-level static approximate adders : a comparative analysis |
title_fullStr |
Gate-level static approximate adders : a comparative analysis |
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Gate-level static approximate adders : a comparative analysis |
title_sort |
gate-level static approximate adders : a comparative analysis |
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2021 |
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https://hdl.handle.net/10356/153402 |
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