High throughput/gate AES hardware architectures based on datapath compression

• Main Authors: Ueno, Rei, Homma, Naofumi, Morioka, Sumio, Miura, Noriyuki, Matsuda, Kohei, Nagata, Makoto, Bhasin, Shivam, Mathieu, Yves, Graba, Tarik, Danger, Jean-Luc
• Other Authors: Nanyang Technopreneurship Center
• Format: Article
• Language: English
• Published: 2022
• Subjects: Engineering::Electrical and electronic engineering; Hardware Architectures; Round-Based Encryption Architecture
• Online Access: https://hdl.handle.net/10356/154464
• Institution: Nanyang Technological University

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and In...