Variation tolerant sensing circuits for resistive memory

• Main Author: Liu, Runbo
• Other Authors: Kim Tae Hyoung
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/154588
• Institution: Nanyang Technological University

Due to the rapid growing of memory market, many new types of NVMs has been made for different advantages, RRAM is one of them. RRAM has the advantages of simple structure, small cell area, low power consumption, easy equal scale reduction and compatibility with standard CMOS process. There fore, it has attracted more and more attention and become a research hotspot. Memory has the advantages of dynamic memory cost, high-speed reading and writing speed and its own nonvolatile characteristics. It is expected to become a general memory. In the design process of RRAM device, its peripheral cir cuit is a crucial part, and SA greatly affects the performance of its peripheral circuit. SA plays an important role in reading operation as well. SA deter mines the accuracy and speed of data reading of the whole device. However, R ratio and different corner have great uncertainty. Therefore, this dissertation focuses on using the Parallel Series Reference cell structure to replace the cur rent reference cell in the traditional SA to overcome high R ratio between high resistance state and low resistance state. Moreover, making sure the sensing cir cuit can work normally under different corner. Also, the TSMC65nm process library is used to the circuit design of the entire SA to achieve a variation tolerant sensing circuir for resistive memory.