Low power PWM based sensor readout circuit

• Main Author: He, Shengyu
• Other Authors: Goh Wang Ling
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/155548
• Institution: Nanyang Technological University

The PWM-based semi-digital sensor interface circuit is highly desirable in low-voltage and low-power applications. Since the PWM technique converts sensor signal amplitude into the change in period, this method is simpler than the analog sensor interface circuit. Comparator serves a vital role in generating PWM signal. In this design, the continuous-time autozero nulling topology will be incorporated to cancel the offset voltage, which has a non-neglected effect on the performance of the comparator, especially in low-voltage conditions. Using the Global Foundry 0.18 μm CMOS technology, a folded-cascode amplifier and an inverter-based amplifier are designed based on the Cadence Virtuoso IC design tool to generate the PWM wave. The feedback loop in this continuous-time autozero nulling architecture has been amended to consume less power. The function of this technique with these two kinds of amplifiers is verified. For the folded-cascode amplifier case, the offset voltage that can be canceled is no less than 5mV. The structure accomplished by the folded-cascode amplifier is capable to work with the minimum voltage of 1.0 volt and the power is around 0.97µW. The structure realized by the inverter-based amplifier consumes power of about 1.59µW with the ability to cope with offset voltage of 60µV under 1.0-volt supply voltage.