Experimental investigation on the performance of ArSMART NoC architecture

The Network on Chip (NoC) architecture is a communication architecture used as a communication subsystem between various Processing Elements (PEs) in a System-on-Chip (SoC) architecture. The NoC architecture provides promising benefits such as high performance, scalability, redundancy, and relative...

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Main Author: Winson, Marvin
Other Authors: Weichen Liu
Format: Final Year Project
Language:English
Published: Nanyang Technological University 2022
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Online Access:https://hdl.handle.net/10356/156567
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-1565672022-04-20T07:04:38Z Experimental investigation on the performance of ArSMART NoC architecture Winson, Marvin Weichen Liu School of Computer Science and Engineering liu@ntu.edu.sg Engineering::Computer science and engineering::Hardware::Performance and reliability The Network on Chip (NoC) architecture is a communication architecture used as a communication subsystem between various Processing Elements (PEs) in a System-on-Chip (SoC) architecture. The NoC architecture provides promising benefits such as high performance, scalability, redundancy, and relative simplicity by utilizing concepts and techniques commonly found in computer networks. The ArSMART NoC - which is an improvement to the SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) NoC - allows transmission of unconflicted flits over distance PEs in one cycle by establishing a bypass link between each cycle with clockless repeaters. On the SMART NoC, link contention prevents lower priority flits from utilizing the bypass. In order to overcome this, the ArSMART NoC allows arbitrary-turn transmission by delegating the task of route computation to a set of cluster controllers that each manages a subset of the available PEs (in contrast to the cycle-by-cycle table-lookup route arbitration on the SMART NoC). This project simulates the performance of the ArSMART NoC architecture under varying conditions. The number of tasks, in-out degree of nodes, execution time, link latency, and Application Injection Rate degrees are varied. Then the performance of the XY Routing algorithm, the Odd Even routing algorithm, as well as a custom arbitrary turn routing algorithm is simulated and evaluated. The simulation is run on the Gem5 simulator, that has been patched to support the ArSMART NoC architecture and are automated through the use of python scripts. Overall, the algorithm that leverages the arbitrary turn capability provided by ArSMART was able to consistently perform better than both XY and OE routing algorithms throughout 2700 randomly generated task graphs. We were able to reach as high as over 22% latency reduction and 35% contention reduction before plateauing at higher task counts. Bachelor of Engineering (Computer Engineering) 2022-04-20T07:04:37Z 2022-04-20T07:04:37Z 2022 Final Year Project (FYP) Winson, M. (2022). Experimental investigation on the performance of ArSMART NoC architecture. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/156567 https://hdl.handle.net/10356/156567 en SCSE21-0168 application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Computer science and engineering::Hardware::Performance and reliability
spellingShingle Engineering::Computer science and engineering::Hardware::Performance and reliability
Winson, Marvin
Experimental investigation on the performance of ArSMART NoC architecture
description The Network on Chip (NoC) architecture is a communication architecture used as a communication subsystem between various Processing Elements (PEs) in a System-on-Chip (SoC) architecture. The NoC architecture provides promising benefits such as high performance, scalability, redundancy, and relative simplicity by utilizing concepts and techniques commonly found in computer networks. The ArSMART NoC - which is an improvement to the SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) NoC - allows transmission of unconflicted flits over distance PEs in one cycle by establishing a bypass link between each cycle with clockless repeaters. On the SMART NoC, link contention prevents lower priority flits from utilizing the bypass. In order to overcome this, the ArSMART NoC allows arbitrary-turn transmission by delegating the task of route computation to a set of cluster controllers that each manages a subset of the available PEs (in contrast to the cycle-by-cycle table-lookup route arbitration on the SMART NoC). This project simulates the performance of the ArSMART NoC architecture under varying conditions. The number of tasks, in-out degree of nodes, execution time, link latency, and Application Injection Rate degrees are varied. Then the performance of the XY Routing algorithm, the Odd Even routing algorithm, as well as a custom arbitrary turn routing algorithm is simulated and evaluated. The simulation is run on the Gem5 simulator, that has been patched to support the ArSMART NoC architecture and are automated through the use of python scripts. Overall, the algorithm that leverages the arbitrary turn capability provided by ArSMART was able to consistently perform better than both XY and OE routing algorithms throughout 2700 randomly generated task graphs. We were able to reach as high as over 22% latency reduction and 35% contention reduction before plateauing at higher task counts.
author2 Weichen Liu
author_facet Weichen Liu
Winson, Marvin
format Final Year Project
author Winson, Marvin
author_sort Winson, Marvin
title Experimental investigation on the performance of ArSMART NoC architecture
title_short Experimental investigation on the performance of ArSMART NoC architecture
title_full Experimental investigation on the performance of ArSMART NoC architecture
title_fullStr Experimental investigation on the performance of ArSMART NoC architecture
title_full_unstemmed Experimental investigation on the performance of ArSMART NoC architecture
title_sort experimental investigation on the performance of arsmart noc architecture
publisher Nanyang Technological University
publishDate 2022
url https://hdl.handle.net/10356/156567
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