SRAM-based in-memory computing for machine learning applications
In memory computing has become popular recently. It not only could accelerate the AI application on hardware, but also could solve the Neumann problem. In this field, digital SRAM design for machine learning has received a lot of attention due to its easy design and high accuracy characteristics. In...
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| 格式: | Thesis-Master by Coursework |
| 語言: | English |
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Nanyang Technological University
2022
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/156761 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | In memory computing has become popular recently. It not only could accelerate the AI application on hardware, but also could solve the Neumann problem. In this field, digital SRAM design for machine learning has received a lot of attention due to its easy design and high accuracy characteristics. In this paper, a 4k weight-selective digital SRAM design is implemented with improvements on Bitcell and Adder Tree. It uses TG logic in the design to improve the speed and eliminate power consumption. The weight-Selective function is used to adapt to the different complexity of the calculation. The simulation is done by using the TSMC65LP process. The Bitcell Array is 64x64, GOPS is 409.6 and the frequency is 200MHz. |
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